The long-anticipated Foenix Core Update has arrived, as Stefany Allaire unveils significant improvements for the F256K2 and F256Jr2 second-generation systems. In a new video, she introduces a redesigned, paid IP core packed with performance upgrades, expanded features, and a reimagined CPU-to-graphics bandwidth strategy—making this release a milestone for the Foenix retro FPGA lineup.
Right from the start, Stefany explains the rationale behind the previous CPU speed limitations and how the Foenix Core Update addresses them. By doubling the CPU’s memory bandwidth from 12.5% to 25%, the system now leverages a 16-bit SRAM bus, allowing twice the data throughput with no sacrifice to Vicky’s graphical performance. This improvement directly boosts both graphical capability and CPU speed.
Additionally, this update empowers developers with more flexible MMU configurations and full 24-bit address space access for the WDC 65C816. Stefany also introduces exciting new features like an external-memory-driven text mode—ideal for NitrOS-9—and automated line drawing directly into the bitmap layer. These additions expand what’s possible in user applications, all while keeping performance tight.
The DMA controller gets a boost too, but with a caveat: data transfers must occur on even memory addresses to maintain efficiency. Also, sprite handling now supports 128 sprites—though it shares time with the new line drawing system, meaning users will need to manage trade-offs.
Looking forward, Stefany discusses plans for adding triangle drawing, collision detection, improved audio DMA, and more. The Foenix Core Update will be offered as a one-time paid upgrade, with discounts based on existing subscriptions.
This release isn’t just about specs—it’s a vital funding initiative to sustain the Foenix ecosystem. Stefany encourages supporters to get involved, share feedback, and help shape the platform’s future.
Foenix users now have more power at their fingertips—and more opportunity to influence what comes next.
